Direct-mapped cache design with a 32-bit address

5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. HW 5.3 table. Bits 31-10 are the tag. Bit 9-5 are the Index. Bits 4-0 are the offset. 5.3.1 [5] What is the cache block size (in words)? 5.3.2 [5] How many entries does the cache have? 5.3.3 [5] What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Table of bytes addressed cache references: 0, 4, 16, 132, 232, 160, 1024, 30, 140, 3100, 180, 2180. 5.3.4 [10] How many blocks are replaced? 5.3.5 [10] What is the hit ratio? 5.3.6 [10] List the final state of the cache, with each valid entry represented as a record of .